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Design and Analysis of Burn-in for Semiconductor Devices
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Introduction |
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An inherent characteristic in semiconductor devices that exhibit a higher failure rate in their early operating life has been long recognized. Appropriate effort/test must be put in place during production to prevent premature failures of devices in the field. Burn-in has been widely used to address this issue. However, through process improvement and better understanding of process technologies, the requirement for burn-in in mature devices and processes has been reduced significantly. Nevertheless, for newly-introduced process technologies and products, the time to market pressure has prompted manufacturers to resort to using burn-in as a viable approach to move new products out to the market quickly, whilst awaiting effort to acquire more knowledge to eliminate or reduce burn-in to meet a specific target annual field return rate.
The course will look at the various aspects of burn-in, with particular focus on the design of burn-in with respect to the burn-in condition and duration determination, effectiveness study and cost analysis. |
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Course Objectives |
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The nature of burn-in
The various aspect in determine burn-in time
The method to shorten burn-in time
Burn-in data analysis
Various documents for burn-in
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Course Outline |
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1. Introduction
Why we need burn-in
How burn-in works
The basic time-to-failure pattern of components
Burn-in definitions, difference between burn-in and environmental stress screening
2. Burn-in methods and document
Various type of burn-in methods including static burn-in, dynamic burn-in, sequential burn-in, multilayer burnin, Barlows method, Markovian Burn-in
Mil-Std and Mil-HDBK relating to burn-in
3. Analysis of burn-in test data
Analyze the burn-in test data using reliability model and mixture distributions methodology to extract distribution parameters
The application of these data for burn-in decisions
4. Burn-in time determination
Various methods of determining the burn-in time to meet different objectives, namely
- To achieve a specified failure rate
- To achieve a specified reliability goals
- To achieve a minimum cost and burn-in efficiency
Graphical and analytical analysis methods for burn-in time determination
The concept of mean residual life for burn-in time determination
5. Accelerated Burn-in
the burn-in time reduction algorithm using accelerated environment conditions such as temperature, voltages and temperature cycling etc.
6. Planning and controlling Production Burn-in
Bringing together the knowledge learnt in previous section and provide a typical systematic "cook-book" approach to the planning of burn-in procedure for their companies products. This includes burn-in planning during the product design phase and the pre-production phase, the execution and control of production burn-in.
Course Methodology
This course is presented classroom style, with case studies to illustrate the concepts taught.
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Trainer(s) |
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Associate Professor Tan, Cher Ming |
Dr. Tan Cher Ming obtained his Electrical Engineering Degree from the National University of Singapore on 1984, and M.A. Sc and Ph.D in Electrical Engineering from the University of Toronto, Canada on 1987 and 1992 respectively. He has worked in the industry on reliability and failure analysis for 10 years before joining Nanyang Technological University. The companies he has worked with are Fairchild Semiconductor, Hewlett Packard, LiteOn Power Semiconductor (Taiwan), Chartered Semiconductor Mfg.
His research work is on Reliability engineering and failure analysis, nano-technology, power semiconductor, wafer bonding. He has published 150 papers in International Journal and Conferences. He has been invited to give several talks on reliability to the industry, and given a keynote speech in International Congress on Micro-reliability and Nano-reliability.
He is the immediate past Chair of IEEE Singapore Section, Chair of IEEE Nanotechnology Chapter in Singapore, Adjunct Senior Scientist in SIMTech, Fellow of Singapore Quality Institute, and Senior member in both the IEEE and ASQ. He was also awarded the first Distinguish Professor in Asia by Mathwork Inc. USA, and listed in Whos Who in the World as well as Marquis Whos Who in Science and Engineering, USA. He is also a reviewer of many international Journals, Chair of several International Conferences. He is the Chair of the Certified Reliability Engineers Program in the Singapore Quality Institute since 1999.
He is continuing giving consultation to industry in the area of reliability. Examples of some companies are Applied Materials, Delphi Automotive, Infineon Asia Pacific, Vestas R&D etc. He has also assisted RSAF to set up their electronic failure analysis Lab. |
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Who Should Attend |
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Process engineers
QA engineers
Product engineers
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Course Details |
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Date: |
20 to 22 July 2009 |
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Time: |
9:00am to 5:00pm |
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Venue: |
NTU@one-north campus, Executive Centre |
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Closing Date: |
6 July 2009 |
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Fee: |
Standard: SGD$980
Alumni: SGD$784 Group (3 & Above): SGD$882 |
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Registration fees inclusive of:
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Online Registration |
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>> CLICK HERE to Register Online
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Methods of Payment |
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1.
Credit Card (Visa and Mastercard only)
2. Cheque
made payable
to Nanyang Technological University
3. Invoice to
Company (for Company Sponsored Participants)
4. E-invoice (for
Government Organizations)
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Cancellation & Refund Policy |
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Written notification to
cce@ntu.edu.sg or fax: (+65) 6774 2911 at least 10 days before course commencement |
No cancellation charges
(Full refund) |
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Written notification within 4 9 days before course commencement |
50% of course fees
(50% refund) |
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Written notification within 3 days before course commencement |
100% of course fees
(No refund) |
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